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| White Electronic Designs 512MB- 64Mx64 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power Supply: 2.5V 0.20V JEDEC standard 200 pin SO-DIMM package W3EG6465S-D4 PRELIMINARY* DESCRIPTION The W3EG6465S is a 64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of eight 64Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change without notice. OPERATING FREQUENCIES DDR266 @CL=2 Clock Speed CL-tRCD-tRP 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-3-3 DDR200 @CL=2 100MHz 2-2-2 May 2004 Rev. 3 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VREF VREF VSS VSS DQ0 DQ4 DQ1 DQ5 VCC VCC DQS0 DQM0 DQ2 DQ6 VSS VSS DQ3 DQ7 DQ8 DQ12 VCC VCC DQ9 DQ13 DQS1 DQM1 VSS VSS DQ10 DQ14 DQ11 DQ15 VCC VCC CK0 VCC CK0# VSS VSS VSS DQ16 DQ20 DQ17 DQ21 VCC VCC DQS2 DQM2 DQ18 DQ22 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol VSS VSS DQ19 DQ23 DQ24 DQ28 VCC VCC DQ25 DQ29 DQS3 DQM3 VSS VSS DQ26 DQ30 DQ27 DQ31 VCC VCC NC NC NC NC VSS VSS DQS8 NC NC NC VCC VCC NC NC NC NC VSS VSS CK2* VSS CK2*# VCC VCC VCC CKE1* CKE0 NC NC A12 A11 Pin 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Symbol A9 A8 VSS VSS A7 A6 A5 A4 A3 A2 A1 A0 VCC VCC A10/AP BA1 BA0 RAS# WE# CAS# CSO CS1* NC NC VSS VSS DQ32 DQ36 DQ33 DQ37 VCC VCC DQS4 DQM4 DQ34 DQ38 VSS VSS DQ35 DQ39 DQ40 DQ44 VCC VCC DQ41 DQ45 DQS5 DQM5 VSS VSS Pin 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Symbol DQ42 DQ46 DQ43 DQ47 VCC VCC VCC CK1# VSS CK1 VSS VSS DQ48 DQ52 DQ49 DQ53 VCC VCC DQS6 DQM6 DQ50 DQ54 VSS VSS DQ51 DQ55 DQ56 DQ60 VCC VCC DQ57 DQ61 DQS7 DQM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VCC VCC SDA SA0 SCL SA1 VCCSPD SA2 VCCID NC W3EG6465S-D4 PRELIMINARY PIN NAMES A0 - A12 BA0-BA1 DQ0-DQ63 DQS0-DQS8 CK0, CK1 CK0#, CK1# CKE0 CS0# RAS# CAS# WE# DQM0-DQM7 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC *Not Used Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock Input Clock Input Clock Enable Input Chip select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply (2.5V) Power Supply for DQS (2.5V) Ground Power Supply for Reference Serial EEPROM Power Supply (2.3V to 3.6V) Serial data I/O Serial clock Address in EEPROM VCC Identification Flag No Connect May 2004 Rev. 3 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM CS0# DQS0 DQM0 DM CS# DQS W3EG6465S-D4 PRELIMINARY DQS7 DQM7 DM CS# DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS2 DQM2 DQ0 DQ1 DQ2 U1 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS3 DQM3 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS1 DQM1 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U5 DM CS# DQS DM CS# DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS4 DQM4 DQ0 DQ1 DQ2 U2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U6 DM CS# DQS DM CS# DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS6 DQM6 DQ0 DQ1 DQ2 U3 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U7 DM CS# DQS DM CS# DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 U4 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U8 120 BA0, BA1 A0-A12 RAS# CAS# CKE0 WE# BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMs WE#: DDR SDRAMs CK0 CK0# 120 CK1 CK1# DDR SDRAM X 4 DDR SDRAM X 4 SERIAL PD SCL WP A0 A1 A2 SA0 SA1 SA2 SDA VDDSPD VDD VREF VSS SPD DDR SDRAMs DDR SDRAMs DDR SDRAMs NOTE: All resistor values are 22 ohms unless otherwise specified. May 2004 Rev. 3 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. W3EG6465S-D4 PRELIMINARY Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -0.5 to 3.6 -1.0 to 3.6 -55 to +150 8 50 Units V V C W mA DC CHARACTERISTICS 0C TA 70C, VCC = 2.5V 0.2V Symbol VCC VCCQ VREF VTT VIH VIL VOH VOL Parameter Supply Voltage Supply Voltage Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Min 2.3 2.3 VCCQ/2 - 50mV VREF - 0.04 VREF + 0.15 -0.3 VTT + 0.76 -- Max 2.7 2.7 VCCQ/2 + 50mV VREF + 0.04 VCCQ + 0.3 VREF - 0.15 -- VTT - 0.76 Unit V V V V V V V V CAPACITANCE TA = 25C, f = 1MHz, VCC = 3.3V, VREF =1.4V 200mV Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#, CAS#, WE#) Input Capacitance (CKE0) Input Capacitance (CK0,CK0#) Input Capacitance (CS0#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Max 29 29 29 26 29 8 29 8 Unit pF pF pF pF pF pF pF pF May 2004 Rev. 3 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs IDD SPECIFICATIONS AND TEST CONDITIONS W3EG6465S-D4 PRELIMINARY Recommended operating conditions, 0C TA 70C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V Parameter Symbol Conditions One device bank; Active - Precharge; tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power- down mode; tCK=tCK(MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. Vin = Vref for DQ, DQS and DM. One device bank active; Power-down mode; tCK(MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continous burst; One device bank active;Address and control inputs changing once per clock cycle; tCK=tCK(MIN); Iout = 0mA. Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. tRC=tRC(MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. DDR266@CL=2 DDR266@CL=2.5 DDR266@CL=2 DDR200@CL=2 Max Max Max Max 2-2-2 2.5-3-3 2-3-3 2-2-2 Units Operating Current IDD0 1320 1320 1320 1320 mA Operating Current IDD1 1520 1520 1520 1520 mA Precharge PowerDown Standby Current IDD2P 48 48 48 48 mA Idle Standby Current IDD2F 400 400 400 400 mA Active Power-Down Standby Current IDD3P 400 400 400 400 mA Active Standby Current IDD3N 760 760 760 760 mA Operating Current IDD4R 1760 1760 1760 1760 mA Operating Current IDD4W 2000 2000 2000 2000 mA Auto Refresh Current Self Refresh Current IDD5 IDD6 2480 40 2480 40 2480 40 2480 40 mA mA Operating Current IDD7A 3840 3840 3840 3840 mA May 2004 Rev. 3 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT : ONE BANK 1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst W3EG6465S-D4 PRELIMINARY IDD7A : OPERATING CURRENT : FOUR BANKS 1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst 4. 4. * * * * Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 May 2004 Rev. 3 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ORDERING INFORMATION FOR D4 Part Number W3EG6465S262D4C W3EG6465S263D4C W3EG6465S265D4C W3EG6465S202D4C Speed 133MHz/266Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 100MHz/200Mb/s CAS Latency 2 2 2.5 2 tRCD 2 3 3 2 tRP 2 3 3 2 W3EG6465S-D4 PRELIMINARY Height* 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C PACKAGE DIMENSIONS FOR D4 67.56 (2.666) MAX C27 R17 R5 R18 R19 R20 R9 R10 R2 R11 R12 R13 3.81 (0.150) MAX. R6 R7 R16 R15 3.98 0.1 (0.157 0.004) R14 U3 U5 U7 U9 R4 U1 C28 R3 31.75 (1.25) 20 (0.787) R8 C29 C3 RP1 RP5 RP9 C5 RP14 C2 RP18 RP13 RP19 C3 R21 C6 RP4 RP7 C18 RP12 C7 RP20 RP22 C8 C26 2.31 (0.091) REF. 4.19 (0.165) 1.80 (0.071) 11.40 (0.449) 47.40 (1.866) 3.98 (0.157) MIN. 1.0 0.1 (0.039 0.004) * ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES) May 2004 Rev. 3 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 512MB- 64Mx64 DDR SDRAM UNBUFFERED W3EG6465S-D4 PRELIMINARY Revision History Rev # Rev 1 Rev 2 Rev 3 History Created Datasheet Change package drawing 3.1 Removed "ED" from part marking Release Date 3-27-02 2-6-03 5-04 Status Advanced Advanced Preliminary May 2004 Rev. 3 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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